In recent years, liquid crystal display devices are used in a wider field of PDAs, OA, and TV sets. Particularly for small portable devices, liquid crystal display devices are widely used far ahead of other kinds of display devices.
In this field, portability is particularly important and thus miniaturization and low power consumption are demanded. Further, a larger screen panel is demanded for visibility. As a matrix liquid crystal panel has a larger screen, a scanning electrode driving device for driving a liquid crystal display panel increases in voltage, resulting in higher power consumption.
One solution for reducing power consumption is to reduce the withstand voltage of the scanning electrode driving device. A driving method and a driving circuit are available which use a power supply oscillating method described in Japanese Unexamined Patent Publication No. 2001-282208.
Referring to FIGS. 5 and 6, the following will describe the driving circuit using a power supply oscillating method shown in FIG. 12 of Japanese Unexamined Patent Publication No. 2001-282208.
FIG. 5 shows a voltage conversion circuit of the conventional art that is constituted of PMOS transistors 515 and 516 and NMOS transistors 517, 518, 519, and 520.
The PMOS transistor 515 has the gate connected to signal input unit 530 and the source and back gate connected to a potential VDD, which is at the “H” level of a direct-current power supply having a low voltage. VDD is the “H” level potential of an input signal of the external system.
The PMOS transistor 516 has the gate connected to an “L” level potential VSS of the direct-current power supply having a low voltage, the source connected to the signal input unit 530, and the back gate connected to the potential VDD. VSS is the ground potential of the external system.
In the above description, “H” level indicates a high level, that is the high potential side of a signal. “L” level indicates a low level, that is the low potential side of a signal. These definitions are applied also in the following description.
The NMOS transistor 517 has the gate connected to the potential VDD, the drain connected to the drain of the PMOS transistor 516, and the back gate connected to a potential VL of an internal circuit. The potential VL is the ground potential applied in the circuit.
The NMOS transistor 518 has the gate connected to the potential VDD, the drain connected to the drain of the PMOS transistor 515, and the back gate connected to the ground potential VL.
The NMOS transistor 519 has the gate connected to the drain of the PMOS transistor 516, the drain connected to the source of the NMOS transistor 518, and the source and back gate connected to the potential VL.
The NMOS transistor 520 has the gate connected to the drain of the PMOS transistor 515, the drain connected to the source of the NMOS transistor 517, and the source and back gate connected to the ground potential VL.
The operations of the circuit shown in FIG. 5 will be described below.
The following will describe the case where a signal having an amplitude between the potential VDD at the “H” level of the external system and the potential VSS at the “L” level of the external system (VDD−VSS) is inputted as a signal of the signal input unit 530 that is an input signal from the external system.
First, when the input of the signal input unit 530 has the potential VDD, the PMOS transistor 515 is turned off and the PMOS transistor 516 is turned on. Thus, the potential VDD is applied to the gate of the NMOS transistor 519 and the NMOS transistor 519 is turned on.
On the other hand, the potential VDD is applied to the gate of the NMOS transistor 517 and the NMOS transistor 517 is turned on with a certain resistance. The NMOS transistor 517 has the function of suppressing through current when the PMOS transistor 516 and the NMOS transistor 520 are turned on/off.
Moreover, the gate of the NMOS transistor 520 has a low potential substantially equal to the ground potential VL, so that the NMOS transistor 520 is turned off. As a result, a signal 540 has a low potential.
The following will describe operations performed when the input unit 530 has the input potential VSS.
When VSS (low potential) is inputted to the input unit 530, the PMOS transistor 515 is turned on and the PMOS transistor 516 is turned off. Then, VDD is applied to the gate of the NMOS transistor 520 and the NMOS transistor 520 is turned on. On the other hand, VDD is applied to the gate of the NMOS transistor 518 and the NMOS transistor 518 is turned on with a certain resistance. The NMOS transistor 518 has the function of suppressing through current when the PMOS transistor 515 and the NMOS transistor 519 are turned on/off. Further, the gate of the NMOS transistor 519 has a low potential substantially equal to the ground potential VL, so that the NMOS transistor 519 is turned off. As a result, the signal 540 has a high potential. Hence, conversion can be performed from a signal having an amplitude between VDD and VSS (VDD−VSS) to a signal having an amplitude between VDD and VL (VDD−VL) With the on resistance of the NMOS transistor 517 and the NMOS transistor 518, it is possible to suppress through current when the PMOS transistor 515 and the NMOS transistor 519 are turned on/off or the PMOS transistor 516 and the NMOS transistor 520 are turned on/off, thereby reducing current consumption and preventing a break caused by heat generated by the transistor.
FIG. 6 shows an example of the potential level of an input signal relative to a potential of the power supply oscillating method according to the conventional art.
FIG. 6 shows the “H” level potential VDD of the input signal of the external system, the “L” level potential of the input signal of the external system, that is the ground potential VSS of the external system, and the ground potential VL applied in the circuit. In addition, reference character VH denotes a high oscillating power supply having a high withstand voltage in the circuit and reference character VCC denotes a supply potential having a low withstand voltage in the circuit.
As is evident from FIGS. 1 and 4 of Japanese Unexamined Patent Publication No. 2001-282208 (not shown), the following fact is well known to persons skilled in the art: the signal 540 of FIG. 5 is subjected to voltage conversion from a signal having an amplitude between VDD and VL (VDD−VL) to a signal having an amplitude between VCC and VL (VCC−VL) and is used in the internal circuit, and the signal 540 is further subjected to voltage conversion to a signal having an amplitude between VH and VL (VH−VL) and is used when the signal is outputted to the outside.
In FIG. 6, when the potential VH is at “L” level, the relationship of VH>VDD>VSS>VCC>VL is established. On the other hand, when the potential VH is at “H” level, the relationship of VH>VCC>VDD>VSS>VL is established. The relational expressions with inequality signs do not always have to be satisfied but it is preferable to satisfy the expressions. An actual embodiment of FIG. 6 has a potential relationship expressed as below.                a. (when VH ias at “L” level) VH, VDD>VSS>VCC>VL        b. (when VH is at “H” level) VH>VCC, VDD>VSS>VL        
As shown in FIG. 6, when the potential VH is at “H” level, VCC and VL are also set at “H” level. That is, a potential difference between the potential VH and the potential VL when the potential VH is at “H” level is almost equal to a potential difference between the potential VH and the potential VL when the potential VH is at “L” level.
In this way, although the potential VH or the potential VL is changed, a potential difference is constant between the potential VH and the potential VL. A power supply configured thus is referred to as an oscillating power supply.